Cadence expands partnership with TSMC on certified tool flows, silicon-proven UALink IP for advanced nodes
Bitget2026/09/23 19:00- Cadence expanded its partnership with TSMC to deliver certified design tools and silicon-proven IP for advanced AI and HPC chips.
- Tool flows gained certification for TSMC’s A14, A16, N2P nodes, targeting faster tape-outs and improved power, performance, area.
- Partnership also supports TSMC 3DFabric wafer-scale, multi-chiplet design flows, including certified die-to-die auto-routing for CoWoS architectures.
- Cadence highlighted UALink IP demonstrated on N3P; UCIe-64G taped out on A14; additional IP development extends into Q4 2026.
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